Digital Circuit Design
数字电路设计是电气与电子类专业的核心基础课程，讲授数字逻辑与数字系统的分析设计方法。课程内容包括数制与码制、逻辑代数与化简、组合逻辑电路分析与设计、触发器与时序逻辑电路、计数器与寄存器、同步与异步状态机、可编程逻辑器件与硬件描述语言 Verilog HDL。通过本课程学习，学生能够独立完成中等复杂度数字系统的设计，为后续嵌入式与计算机体系结构课程奠定基础。
Digital Circuit Design is a core foundational course for electrical and electronic majors, teaching analysis and design methods for digital logic and systems. Topics include number systems and codes, Boolean algebra and simplification, combinational logic design, flip-flops and sequential circuits, counters and registers, synchronous and asynchronous state machines, programmable logic devices, and Verilog HDL. Students learn to design moderately complex digital systems, preparing for embedded systems and computer architecture.
学生使用 Verilog HDL 在 Basys3 FPGA 开发板上设计具有时、分、秒计时功能的多功能数字钟，支持按键校时、整点报时与 24/12 小时制切换。要求完成 RTL 代码、约束文件与时序仿真，下载到开发板验证功能，提交设计报告、源代码与演示视频。
Students use Verilog HDL on a Basys3 FPGA board to design a multi-function digital clock with hour, minute, second counting, button-based time setting, hourly chime, and 24/12-hour mode switching. They complete RTL code, constraint files, and timing simulation, download to the board for verification, and submit a design report, source code, and demo video.